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21154 pci-to-pci bridge specification update july 2004 notice: the 21154 may contain design defects or errors known as errata which may cause the behavior of the 21154 to deviate from published specifications. current characterized errata are documented in this specification update. order number: 278295-017
21154 pci-to-pci bridge specification update information in this document is provided in connection with intel? products. no license, express or implied, by estoppel or otherwise, to any intellectual property righ ts is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. intel products are not intended for use in medical, life saving, life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel' s website at http://www.intel.com. copyright ? intel corporation, 2005 intel is a trademark or registered trademark of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others.
21154 pci-to-pci bridge specification update iii contents revision history ......................................................................................... 5 preface....................................................................................................... 8 summary table of changes..................................................................... 10 identification information.......................................................................... 14 errata ....................................................................................................... 15 specification changes ............................................................................. 22 specification clarifications ....................................................................... 23 documentation changes ......................................................................... 24

21154 pci-to-pci bridge specification update intel confidential5 revision history date version description july 2004 017 updated errata 9. description. 2/25/05 016 the following changes have been made in this version: ? updated status for errata 7. and errata 9. on page 11 . ? revised pin 1 designator change description in ?specification changes? on page 11 . ? added errata 10. ?secondary address pins ar e driven incorrectly during reset.? on page 21 . ? added documentation change ?updated version of pci local bus specification? on page 36 . 3/1/02 015 the following changes have been made in this specification update: ? updated errata table status column on page 11 . updated status for erratas 1 through 6. ? added recommendation #1 fix for errata 6 ?secondary clocks outputs s_clk_o<9:0> may not start-up properly under some conditions? . moved previously existing fix recommendation for errata 6 to become the second recommendation. ? added errata 9 , ?21154ae/be may experience performance problems or hangs when p_vio = 3.3v? on page 20 . ? updated specification clarification 1 title description on page 23 . ? updated links in this document. 6/25/01 014 updated errata #1 description in table , ?errata? on page 11 and added new worst-case conditions tables for tval description, section 1 on page 15 6/8/01 013 updated errata #1 title description in table , ?errata? on page 11 and added worst-case conditions for tval description, section 1 on page 15
6intel confidential 21154 pci-to-pci bridge specification update revision history 5/8/01 012 added information for ae and be versions of the 21154 product updated errata #5 ac marking state in table , ?errata? on page 11 updated status state for errata #4, #5, #6, and #8 in table , ?errata? on page 11 and in descriptions in ?errata? on page 15 updated descriptions for errata #1 and #3 in table , ?errata? on page 11 added last two rows to table 1, ?21154 markings? on page 14 updated description for ?tval timing issues when running at 66 mhz for all pci signals. tval timing improved on the 21154be.? on page 15 updated description for ?hold time issues for all pci signals (both bused and control) on the 21154.? on page 16 added changes #2, #3, and #4 in ?specification changes? on page 22 added to table , ?documentation changes? on page 13 that include: ? ?updated version of pci local bus specification? on page 35 ? ?section 4.1, updated s_clk and p_clk description? on page 35 ? ?section 4.2, updated clock outputs? on page 35 ? ?section 4.4.1, added note at end of section.? on page 35 ? ?section 4.5, table 5 product part numbers have been updated.? on page 36 . note: these documentation changes have been implemented in version 003 of the 21154 pci-to-pci bridge hardware implementation application note . 4/30/01 011 the steppings columns in the ?errata? table, ?specification changes? table, and ?specification clarifications? on page 11 were changed to markings to more accurately reflect the revisions of the component. errata #3 (setup issues with pci control signals when running at 66 mhz on the 21154bc) of this specification update was found to be invalid and is now listed as fixed. the term ?rev_id6? was removed from the problem section of errata 3 , setup issues with pci control signals when running at 66 mhz on the 21154bc. on page 16 . errata 7 , gpio 66 mhz timing may cause secondary clocks to be disabled was added. errata 8 , bus conflict occurs during configuration on agp port of some chip sets. was added. documentation changes 12 , section 10.2, secondary clock control, figure 19 , 15 , and 18 , section 4.4.1, serial clock mask shift, figure 3 were modified, and documentation change 15 , section 10.2.1, mask and load shift timing events for 66 mhz operation was added. 12/15/00 010 documentation changes 17 , 18 , and 19 , referenced the wrong document number. the correct document number has been updated in the summary table of changes . all references to the 21554 have been changed to 21154. figures in documentation changes 13 and 20 have been updated. errata 3 now has stepping c included as an errata in the summary table of changes . 11/13/00 009 corrected speed settings for 21154ab/ac/bc markings . 10/02/00 008 added errata 6 . date version description
21154 pci-to-pci bridge specification update intel confidential7 revision history 9/18/00 007 modified description of trst_l, tms and tdi signal, added a new section on jtag testing. modified the description of the trst_l specification clarification. modified order of serial stream in figure 20, clock mask and load timing. added note for pull-up resistor for output clocks. added specification change to pbga package dimensions for coplanarity maximum value. added documentation changes 21 and 22: descriptions of two signals when secondary bus speed set for 66 mhz. 2/7/00 006 modified order of serial stream in table 34, gpio serial data format. modified the description for dword bit 0. modified figure 19, example of gpio clock mask implementation on the system board. modified figure 20, clock mask and load shift timing. clarified definition of trst_l signal. 12/14/99 005 modified description of the clamp circuit errata. added 64-bit data bus width errata. 9/1/99 004 added documentation change item 6 for 66 mhz operation. updated hold time errata. added clamp circuit errata. 8/11/99 003 tsetup test conditions found to be invalid. device meets 3 ns tsetup limit on all pins. 7/29/99 002 added updated boundary scan order pin list. 7/19/99 001 this is the new specification update docum ent. it contains all identified errata published prior to this date. date version description
8intel confidential 21154 pci-to-pci bridge specification update preface preface this document is an update to the specifications contained in the affected documents/related documents table below. this document is a compilation of device and documentation errata, specification clarifications and changes. it is intended for hardware system manufacturers and software developers of applications, operating systems, or tools. information types defined in nomenclature are consolidated into the specification update and are no longer published in other documents. this document may also contain information that was not previously published. affected documents/related documents title order 21154 pci-to-pci bridge datasheet 278108 21154 pci-to-pci bridge configuration application note 278080 21154 pci-to-pci bridge hardware implementation application note 278081 21154 pci-to-pci bridge evaluation board user?s guide 278133
21154 pci-to-pci bridge specification update intel confidential9 preface nomenclature errata are design defects or errors. these may cause the 21154 pci-to-pci bridge?s behavior to deviate from published specifications. hardware and software designed to be used with any given stepping must assume that all errata documente d for that stepping are present on all devices. specification changes are modifications to the current published specifications. these changes will be incorporated in any new release of the specification. specification clarifications describe a specification in greater detail or further highlight a specification?s impact to a complex design situation. these clarifications will be incorporated in any new release of the specification. documentation changes include typos, errors, or omissions from the current published specifications. these will be incorporated in any new release of the specification. note: errata remain in the specification update throughout the product?s life cycle, or until a particular stepping is no longer commercially available. under these circumstances, errata removed from the specification update are archived and available upon request. specification changes, specification clarifications and documentation changes are removed from the specification update when the appropriate changes are made to the appropriate product specification or user documentation (data sheets, manuals, etc.).
10intel confidential 21154 pci-to-pci bridge specification update summary table of changes summary table of changes the following table indicates the errata, specifica tion changes, specification clarifications, or documentation changes which apply to the 21154 pci-to-pci bridge product. intel may fix some of the errata in a future stepping of the comp onent, and account for the other outstanding issues through documentation or specification changes as noted. this table uses the following notations: codes used in summary table stepping x: errata exists in the stepping indicated. specification change or clarification that applies to this stepping. (no mark) or (blank box): this erratum is fixed in listed stepping or specification change does not apply to listed stepping. n.a. not applicable. page (page): page location of item in this document. status doc: document change or update will be implemented. fix: this erratum is intended to be fixed in a future step of the component. fixed: this erratum has been previously fixed. no fix: there are no plans to fix this erratum. row change bar to left of table row indicates this erratum is either new or modified from the previous version of the document.
21154 pci-to-pci bridge specification update intel confidential11 summary table of changes errata no. markings page status errata ab ac bc ae be 1 n/a n/a x n/a x 15 no fix tval timing issues when running at 66 mhz for all pci signals. tval timing improved on the 21154be. 2 xxxxx 16 no fix hold time issues for all pci signals (both bused and control) on the 21154. 316 fixed setup issues with pci control signals when running at 66 mhz on the 21154bc. 4 xx 16 fixed clamp circuit may not function properly under all conditions 5 xxx 17 fixed 64-bit data bus width not maintained when transitioning from pci bus power management states d3 to d0 6 xx 17 fixed secondary clocks outputs s_clk_o<9:0> may not start-up properly under some conditions 7 n/a n/a x n/a x 19 no fix gpio 66 mhz timing may cause secondary clocks to be disabled 8 n/a n/a x 20 fixed bus conflict occurs during configuration on agp port of some chip sets. 9 xx 20 no fix 21154ae/be may experience performance problems or hangs when p_vio = 3.3v 10 xx 21 no fix secondary address pi ns are driven incorrectly during reset. specification changes no. markings page status specification changes ab ac bc ae be 1 xxxx 22 doc pbga package dimensions for coplanarity changed from maximum value 0.15 mm to maximum value of 0.2 mm 2 xx 22 doc pci configuration space registers have changed. 3 xx 22 doc pin 1 designator change 4 xx 22 doc power management capability change
12intel confidential 21154 pci-to-pci bridge specification update summary table of changes specification clarifications no. markings page status specification clarifications ab ac bc ae be 1 xxxxx 23 doc signal trst_l must be driven low to disable jtag for normal operation
21154 pci-to-pci bridge specification update intel confidential13 summary table of changes documentation changes no. document revision page status documentation changes 1 278108 24 doc section 17.2, table 40, absolute maximum ratings 2 278108 24 doc section 18.0, paragraph 1 3 278108 24 doc section 18.0, figure 25, 304-point 2-layer pbga package 4 278108 24 doc section 18.0, table 51, 304-point 2-layer pbga package dimensions 5 278108 25 doc section 16.2, table 39, boundary scan order 6 278133 28 doc section 4.3, paragraph 1 7 278108 28 doc section 16.7, initialization, paragraph 1 8 278081 28 doc section 5.1, initialization, description 9 278081 29 doc section 6.3.1, signal trst_l pull-down resistor, new section 10 278108 29 doc section 2.10, jtag signals, table 13 11 278080 30 doc section 5.0, system initialization, last paragraph 12 278108 30 doc section 10.2, secondary clock control, figure 19 13 278108 30 doc section 10.2, secondary clock control, figure 20 14 278108 31 doc section 10.2, secondary clock control, table 34 15 278108 31 doc section 10.2.1, mask and load shift timing events for 66 mhz operation 16 278080 32 doc section 15.1.3, primary command register, table description 17 278081 33 doc section 4.4.1, serial clock mask shift, table 4 18 278081 33 doc section 4.4.1, serial clock mask shift, figure 3 19 278081 34 doc section 4.4.1, serial clock mask shift, figure 4 20 278081 34 doc section 4.2, 21154 output clocks 21 278108 35 doc section 18.0, table 51, 304-point 2-layer pbga package dimensions 22 278108 35 doc section 2.5, secondary bus arbitration signals, table 8 23 278108 35 doc section 2.9, miscellaneous signals, table 12 24 278081 35 doc updated version of pci local bus specification 25 278081 35 doc section 4.1, updated s_clk and p_clk description 26 278081 35 doc section 4.2, updated clock outputs 27 278081 35 doc section 4.4.1, added note at end of section. 28 278081 36 doc section 4.5, table 5 product part numbers have been updated. 29 278108 278080 278081 278133 36 doc updated version of pci local bus specification
14intel confidential 21154 pci-to-pci bridge specification update identification information identification information markings the 21154 is a legacy component that was initially introduced by digital semiconductor, a business division of digital equipment corpor ation. the characteristics are described in table 1 . table 1. 21154 markings package markings rev_id register value a a. identified in a pci system by reading the value in the rev_id register. package type speed (mhz) stepping digital semiconductor 21154aa dc1062b 01h 304pbga 33 b digital semiconductor 21154ab dc1062c 02h 304pbga 33 c intel 21154ac dc1113a 05h 304pbga 33 a intel 21154bc dc1113a 05h 304pbga 66 a intel 21154ac dc1113b 05h 304pbga 33 b intel 21154bc dc1113b 05h 304pbga 66 b intel FW21154AE 00h 304pbga 33 e intel fw21154be 00h 304pbga 66 e
21154 pci-to-pci bridge specification update intel confidential15 errata errata 1. tval timing issues when running at 66 mhz for all pci signals. tval timing improved on the 21154be. problem: this problem exists for parts with rev_id 5 and rev_id 0. two worst-case slow conditions exist. the 21154bc and 21154be were tested under two different sets of worst-case slow conditions. table 2. definition of worst case slow conditions table 3. comparison of the 21154bc and the 21154be performance implication: this miss for tval on pci control signals may reduce total flight time (tprop) when running at 66 mhz. the 21154be meets or exceeds the 21154bc performance under the worst-case slow conditions. note: the fw21154be worst case slow condition 2 includes the very slow processing corner, 108 o c junction temperature, no airflow, 4 layer coupon, 3.0 v vdd, and bus switched data (all 1s and all 0s flowing upstream from a fully loaded secondary) with no interrupts. any improvement in the thermal factors (o ja), board design, vdd, data transition density, and interrupt density and tval will be < 6.0 ns at 85 o c junction temperature. workaround: there are no workarounds for this erratum. note: refer to the 21154 pci-to-pci bridge specification update errata table for current errata. all errata listed are fixed in the 21154ae/be version except for errata #1, #2, and #7. status: no fix : see ?summary table of changes? on page 10 . worst-case slow t test [t j ] ( o c) process variation (intel defined) v dd (v) condition 1 85 s - slow 3.0 condition 2 a a. the fw21154be worst case slow condition 2 includes the very slow processing corner, 108 o c junction temperature, no airflow, 4 layer coupon, 3.0 v v dd , and bus switched data (all 1s and all 0s flowing upstream from a fully loaded secondary) with no interrupts. any improvement in the thermal factors (o ja), board design, v dd , data transition density, and interrupt density and tval will be < 6.0 ns at 85 o c junction temperature. 108 ss - very slow 3.0 product worst-case slow condition tval v_v (ns) tval z_v (ns) 21154bc 1 6.5 8.0 21154bc 2 no data no data 21154be 1 <6.4 <6.25 21154be 2 7.35 7.35
16intel confidential 21154 pci-to-pci bridge specification update errata 2. hold time issues for all pci signals (both bused and control) on the 21154. problem: this problem exists for parts with rev_id 2, rev_id 5 and rev_id 0. the pci local bus specification, revision 2.2 , specifies a hold time of 0 ns in section 7.6.4.2. the 21154ab requires a minimum hold time of 1.4 ns. both the 21154ac/bc and 21154ae/be require a minimum hold time of 1.375 ns. implication: most pci devices will function properly with this difference to the hold time specification. workaround: there are no workarounds for this erratum. status: no fix : see ?summary table of changes? on page 10 . 3. setup issues with pci control signals when running at 66 mhz on the 21154bc. problem: this problem was originally believed to exist for parts with rev_id 5. setup time issues on the following 66 mhz pci control signals: p_frame_l, p_irdy_l, p_trdy_l, s_frame_l, s_irdy_l, s_trdy_l. the pci local bus specification, revision 2.2 , specifies a setup time of 3 ns for all devices when running at 66 mhz in section 7.6.4.2. the 21154bc requires a minimum worst-case setup time of 4.5 ns. implication: the tsetup specification miss on pci control sign als must be considered in the overall timing budget for designs that use this product, and may reduce total flight time (tprop) when running at 66 mhz. workaround: this errata was caused by a test-fixture problem and is invalid. status: fixed 4. clamp circuit may not function properly under all conditions problem: this problem has been found on parts with rev_id 5. when either the primary or secondary vio pins are connected to 3.3 volts, the 21154?s clamping circuit may not function properly. implication: dependent on the application environment, oscillations or ?ringing? have been observed on some pci control signals (for example, stop#). the ci rcuitry to generate the input clamp voltages of both the 21154ac and 21154 bc is different than that of the 21154ab. workaround: when the application topology allows it (short bus lengths, direct etch runs), connecting 3.3 volts to these pins should produce desired results. the use of p_vio and s_vio for both the 21154ac and 21154bc will be determined by the customer application. designs that adhere to the ?expansion board specification? of the pci local bus specification, revision 2.2 are not affected. designs whose topology might include long bus lengths might find that connecting s_vio or p_vio to 5 volts leads to improved signal integrity for the corresponding bus. as such, intel recommends thorough signal integrity analyses prior to a decision on which voltage to connect to these pins. if there is any 5-volt pci device on a bus segment, th e vio pin for that segment should be tied to the 5 volt supply. status: fixed
21154 pci-to-pci bridge specification update intel confidential17 errata 5. 64-bit data bus width not maintained when transitioning from pci bus power management states d3 to d0 problem: when transitioning from pci bus power management states d3 hot to d0 hot, the 21154 performs an internal reset of the primary bus circuits a nd clears the req64 status of the primary bus. the secondary bus continues to operate at 64-bit data bus width but the primary bus width reverts back to a 32-bit data bus width. the 21154 drives the ad<63:32> with whatever data is next in its queue and may drive incorrect parity for ad<63:32> as well. implication: the 21154 can cause bus contention on ad<63:32> resulting in data corruption and device damage. this erratum may also cause some systems to hang or report parity errors. workaround: this problem can be avoided by treating the 21154 as a pci bus power management legacy device by not using the pci bus power management capabilities. status: fixed 6. secondary clocks outputs s_clk_o<9:0> may not start-up properly under some conditions note: this errata only applies to applications that use the 21154 for secondary clocks. problem: this problem has been found on the 21154ac and 21154bc. under repeated and frequent power cycling, the secondary clock circuits may not powe r up in the proper state, resulting in the device not coming out of reset after power up. implication: in a system with a 21154ac or 21154bc that has one of its s_clk_o<9:0> outputs fed back to provide the s_cl k, it is possible that the s_clk_o<9:0> output clocks will be driven and remain low, keeping s_rst_l asserted, during system power up. this happens occasionally when a latch whose outpu t disables the serial shift registers on the secondary clock control powers up in a high state and the shift register bit corresponding to the s_clk_o<9:0> output that is fed back also powers up in the high state. workaround: two workarounds are provided for this errata: ? the first is the recommended workaround which ensure proper operation of the secondary clock outputs s_clk_0<0:9>. ? the second workaround ensures the secondary cl ock outputs operate properly but could result in contention between the s_ck l_0 output and the buffer. 1. figure 1 illustrates the first recommendation - a circuit where an on-board pulse source is gated via the b0 input of the multiplexer to the s_clock_in pin of the 21150. at time 0, the s input of the multiplexer is low, allowing pulses from the on-board pulse source, connected to the b0 input, to be provided to the 21150 s_clk input pin. when the time determined by the r/c network is satisfied, the s input pin will be in a logic high state. the multiplexer will then shut off the input pulse from s0 and will direct the s_clock_out pulses via the b1 multiplexer input, into s_clock_in the values used for the r/c network should be selected to allow a minimum of 2 pulses to be delivered to the 21150 after vdd has reached 3.0v at a frequency not to exceed the appropriate pci component. i.e. 30 ns for a 33mhz bridge. these values should be chosen based on the rise time of the power supply and the frequency of the on board pulse source. the values given for r1, r3, and c1 are for example purposes only.
18intel confidential 21154 pci-to-pci bridge specification update errata note: the nc7sb3157 2:1 multiplexer / demultiplexer bus switch used in this example has a maximum propagation delay of 800ps that should be taken into consideration when matching trace lengths of the clock lines to avoid introducing excessive skew in the clocks. all s_clock etch lengths must be matched to within 2ns @ 33mhx or 1ns @66mhz. the addition of this circuit requires that the etch length for the s_clock_in signal be reduced to compensate for the 800ps delay. 2. in the second recommendation, to guarantee the proper initialization of the s_clk circuits, the addition of an external circuit that provides a minimum of two transitions on the s_clk input during the power-up ramp is necessary. this can be done using a solution that drives an external clock onto the s_clk input while 3.3v vcc is ramping during power up. figure 2 illustrates the use of a tristable buffer to provide multiple pulses to the s_clk input. the vcc ramp rate and r1,c1 time constant determine the duration and amplitude of the pulses generated during power up. the r2-r3 values are chosen based on applicable board etch impedance-matching requirements. figure 1. s_clock multiplexer workaround circuit for errata 6. a9661-01 21154 nc7sb3157 c1 .02 uf r1 47k r3 68k r2 33 s s_clk_in s_clk_out a b0 b1
21154 pci-to-pci bridge specification update intel confidential19 errata the following should be considered in calculating the r1,c1 time constant: ? make the time constant of the circuit as short as possible, while still ensuring that a minimum of two pulses are generated during the vcc ramp. ? phase delay between s_clk_o and the external clock should be minimized. ? matching the external clock and s_clk_o frequencies to reduce contention . ? laboratory experiments using p_clk as the external clock and a r1c1 time constant between 40 and 60 percent of the vcc ramp have been successful using this configuration. however the use of p_clk as the external clock violat es the pci bus specification for loading of the primary clock. status: fixed 7. gpio 66 mhz timing may cause secondary clocks to be disabled problem: in the secondary clock control function, the msk_in pin may be used with an external shift register to selectively disable secondary clock ou tput pins. at 66 mhz the timing of the interface between the gpio pins and the external shift regist er may cause some secondary clock outputs to be incorrectly disabled. the setup time of the recommended 74f166 shift register is not compatible with the timing of the gpio<2> , and gpio<0> outputs of the 21154 pci-to-pci bridge. pin gpio<2> driving the shift register load/shift enable ( pe# ), does not provide the necessary setup time for the gpio<0> . signal gpio<0> is used as a clock to initiate the parallel load of the 74f166 shift register data inputs. the timing is referred to as tgsval. note: this errata does not apply when operating at 33 mhz or if the external shift register is not used and msk_in is grounded enabling all secondary clocks. figure 2. recommended circuit for a tristable buffer a8363- 01 r1 r3 v cc c1 s_clk external clock s_clk_o r2
20intel confidential 21154 pci-to-pci bridge specification update errata implication: at 66 mhz the setup time mismatch between the shift register parallel inputs and pe# pin and gpio pins may cause the shift register to be incorrectly loaded. this could result in the secondary clocks to be incorrectly disabled. workaround: in order to provide an appropriate setu p time, a buffer must be added to delay gpio<2> with respect to gpio<0> . this buffer (or buffers) provides the delay for gpio<2> to correctly load the parallel data inputs of 74f166 registers. a setup time of at least 3ns is required at the shift register for pe# to load. note: for more information, see section 10.2.1, mask and load shift timing events for 66 mhz operation in this specification update. status: no fix 8. bus conflict occurs during configuration on agp port of some chip sets. problem: the 21154 bridge accepts type zero configuration cycl es on its primary bus. it also accepts type 1 configuration cycles on its primary bus and forwar ds them, if they are addressed to a bus number between its secondary and subsequent bus numbers, which are assigned to the bridge by system software. the secondary and subsequent bus number registers are set to zero by reset. some chipsets supporting agp use type 1 configuratio n cycles to program them selves. the chipset has set its own address to be bus 0, device 0. unfort unately, this creates a conflict if the bridge's downstream bus number registers have not yet been programmed to a non-zero value. this conflict occurs when both the ch ipset and bridge respond to type one configuration cycles to bus 0 resulting in bus contention. implication: both the agp interface and the 21154 bridge will respond to the same type 1 bus transaction causing bus signal contention. workaround: none status: fixed 9. 21154ae/be may experience performance problems or hangs when p_vio = 3.3v problem: intel has received reports of performance problems due to excessive retries and hangs in a few applications when p_vio and/or s_vio =3.3v. the retry issue has been observed in several types video, fibre channel and gigabit ethernet modules with the time to failure ranging from 7 minutes to 39 hours. the symptom of this issue is that a delayed read is initiated on the primary bus. it is immediately responded to with retry and stored as a cam entry. the request is played out on the secondary bus and the device receives the data. the cam entry b ecomes corrupt due to noise on the core ground. this causes the read request on the primary bus to match the cam entry, but the bridge does not respond with the data. as the cam entry is matched, no additional read request is made on the secondary bus, but the primary bus never receives the data, only retries. this causes the initiating master to continue to retry the read, making no progress. the 21154 will eventually discard that read data when the primary master timeout timer expires (2 10 or 2 15 clock cycles). the delayed read transaction is then reinitiated on the primary bus and usually completes normally. this causes a 30.7 s or 983 s delay (at 33mhz) depending on the setting of the primary master timeout bit. the same issue and scenario has also been reported on delayed reads from the secondary bus to the primary bus. the root cause is due to changes in the internal grounding scheme implemented in the 21154ae/be - an approximate 400mv reduction in the noise immunity occurred in the cam circuitry. the data stored within the cam (content addressable memory) circuitry becomes
21154 pci-to-pci bridge specification update intel confidential21 errata corrupted resulting in a mismatch when the trans action is retried causing the transaction to be retried continuously. the primary master timeout timer times out (2 10 or 2 15 clock cycles), discards the data, and reinitiates the transaction on the next cycle. this transaction usually completes as a normal delayed read transaction. since the 21154 is a highly symmetrical device a nd the cam circuitry is duplicated on both the primary and secondary interfaces the issue may occur on either an upstream or downstream delayed read transactions. implication: applications using p_vio and/or s_vio=3.3v may experience excessive retries due to a reduction in noise immunity in the cam section of the chip. when p_vio and/or s_vio is set above ~3.8v the biasing of the input transistor effectively reduces the resulting core ground undershoot that is coupled through the esd protection clamp. this issue has only been reported in a very small number of high performance applications such as video cards, gigabit ethernet and 100mbyte/s fibre channel with p_vio and/or s_vio set to 3.3v. other lower performance applications and implementations with p_vio and s_vio set to 5v have not reported the issue. this may also manifest as a layout sensitivity issue. workaround: setting p_vio and s_vio to 5v has proven to el iminate these issues on current designs. many 21154 designs that implemented the errata 4 work around are already biasing the p_vio and s_vio pins to 5v and should not experience the issues. note:p_vio and s_vio pins set the value of the voltage clamp only and has no affect on the signaling levels of the bus. status: no fix 10. secondary address pins are driven incorrectly during reset. problem: during reset s_ad <63:0>, c/be# and par are driven high. the pci local bus specification requires that these pins be driven low during reset. implication: in applications where multiple pci components implemented on the secondary bus may drive the bus during reset, there is a potential for device contention if the 21154ae/be is driving high and the other device/devices are driving low. this contention may cause excessive power dissipation in the 21154 and could potentially damage the device. workaround: there is no known work around. status: no fix
22intel confidential 21154 pci-to-pci bridge specification update specification changes specification changes 1. pbga package dimensions for coplanarity changed from maximum value 0.15 mm to maximum value of 0.2 mm per pcn notification 961, the 304-point 2-layer pbga package dimensions for symbol aaa, coplanarity, are changed from maximum value 0.15 mm to maximum value 0.2 mm. note: the following changes (2-4) are specific to the 21154ae/be version of the product only. 2. pci configuration space registers have changed. table 1. register changes 3. pin 1 designator change viewing the text label printed on top of the 21154ae/be package (marking side), the pin 1 designator appears in the lower left hand corner of the package. the pin 1 designator for previous steppings was located in the upper left hand corner of the package. note: the pin designations have not changed. the only change was that the printed label was rotated 90 o . 4. power management capability change the pmeena_l pin was changed on the 21154ae/be to indicate that devices on the secondary side of the bridge do not support the pme# pin. it is up to the software then to scan the device to actually determine pme# pin support. this is described in table 2 that follows: table 2. power management capability changes register offset old value new value vendor id 00:01 1011h 8086h device id 02:03 0026h b154h revision id 08 05h 00h description value pin number d11 previous name vdd previous function power input new name pmeena_l function input operation this can be tied to either vdd or vss (ground). this effects the value of bits [31:27], pme_sup, of the power management register (dword address dch, offset deh). vdd these 5 bits should read a 00000 a , as in previous steppings. a. 00000 indicates that the device behind the bridge does not support pme#. vss these 5 bits should read as 11111.
21154 pci-to-pci bridge specification update intel confidential23 specification clarifications specification clarifications 1. signal trst_l must be driven low to disable jtag for normal operation the signal trst_l resets the jtag circuitry while asserted low. this signal also enables normal jtag tap controller operation when high. for normal pci-to-pci bridge operation, disable jtag by pulling trst_l low using a 5k resistor.
24intel confidential 21154 pci-to-pci bridge specification update documentation changes documentation changes 1. section 17.2, table 40, absolute maximum ratings maximum power p wc is changed from 2.2w to 2.9w. 2. section 18.0, paragraph 1 section 18.0. paragraph 1 is changed to read as follows: the 21154 variants are contained in the 304-point plastic ball grid array (pbga) packages shown in figure 25. the 21154ac/bc and 21154ae/be variants utilize a 4-layer 304-point pbga. all other variants utilize a 2-layer 304-point pbga. 3. section 18.0, figure 25, 304-point 2-layer pbga package section 18.0, figure 25 title is changed to read as follows: 304-point pbga package (2-layer and 4-layer) 4. section 18.0, table 51, 304-point 2-layer pbga package dimensions section 18.0, table 51 title is changed to read as follows: 304-point pbga package dimensions (2-layer and 4-layer) table 40. absolute maximum ratings parameter minimum maximum junction temperature, t j ? 125 o c maximum voltage applied to signal pins ?5.5 v supply voltage, v cc ?3.9 v maximum power, p wc ?2.9 w storage temperature range, t sg -55 o c 125 o c
21154 pci-to-pci bridge specification update intel confidential25 documentation changes 5. section 16.2, table 39, boundary scan order the boundary-scan order pin call outs change from pin r4 through pin r21. the correct pin call out is: table 39. boundary scan order (sheet 1 of 3) pin number signal name boundary scan order by group disable group disable cell r4 bpcce na/127 ? note: a new signal, bpcce, was added on pin r4 for the 21154ab and later revisions. from pin r4 through pin r21, two values are provided in the xxx/yyy format: the boundary-scan register number in the xxx field is for the 21154aa version only, and the boundary- scan register number in the yyy field is for the 21154ab and later revisions. t3 p_clk 127/128 ? t2 v ss 128/129 ? group disable 3 u3 p_req_l 129/130 3 u2 p_ad<31> 130/131 2 u4 p_ad<30> 131/132 2 u1 p_ad<29> 132/133 2 v2 p_ad<28> 133/134 2 v1 p_ad<27> 134/135 2 v3 p_ad<26> 135/136 2 w2 p_ad<25> 136/137 2 w1 p_ad<24> 137/138 2 y2 p_cbe_l<3> 138/139 2 y1 p_idsel 139/140 ? w4 p_ad<23> 140/141 2 y3 p_ad<22> 141/142 2 aa1 p_ad<21> 142/143 2 aa3 p_ad<20> 143/144 2 y4 p_ad<19> 144/145 2 ab3 p_ad<18> 145/146 2 aa4 p_ad<17> 146/147 2 y5 p_ad<16> 147/148 2 ac4 v ss 148/149 ? group disable 2 ab4 p_cbe_l<2> 149/150 2 aa5 p_frame_l 150/151 1 ac5 p_irdy_l 151/152 1 ab5 p_trdy_l 152/153 1 aa6 p_devsel_l 153/154 1 ac6 p_stop_l 154/155 1 ab6 p_lock_l 155/156 1 ?v ss 156/157 ? group disable 1
26intel confidential 21154 pci-to-pci bridge specification update documentation changes ac7 p_perr_l 157/158 1 y7 p_serr_l 158/159 1 ab7 p_par 159/160 0 aa7 p_cbe_l<1> 160/161 0 ab8 p_ad<15> 161/162 0 aa8 p_ad<14> 162/163 0 ac9 p_ad<13> 163/164 0 ab9 p_ad<12> 164/165 0 aa9 p_ad<11> 165/166 0 ac10 p_ad<10> 166/167 0 ab10 p_m66ena 167/168 0 aa10 p_ad<9> 168/169 0 y11 p_ad<8> 169/170 0 ac11 p_cbe_l<0> 170/171 0 ab11 p_ad<7> 171/172 0 aa11 p_ad<6> 172/173 0 aa12 p_ad<5> 173/174 0 ab12 p_ad<4> 174/175 0 ab13 p_ad<3> 175/176 0 aa13 p_ad<2> 176/177 0 y13 p_ad<1> 177/178 0 aa14 p_ad<0> 178/179 0 ab14 p_ack64_l 179/180 0 ac14 p_req64_l 180/181 0 aa15 p_cbe_l<7> 181/182 0 ab15 p_cbe_l<6> 182/183 0 y15 p_cbe_l<5> 183/184 0 ac15 p_cbe_l<4> 184/185 0 aa16 p_ad<63> 185/186 0 ab16 p_ad<62> 186/187 0 aa17 p_ad<61> 187/188 0 ab17 p_ad<60> 188/189 0 y17 p_ad<59> 189/190 0 ab18 p_ad<58> 190/191 0 ac18 p_ad<57> 191/192 0 aa18 p_ad<56> 192/193 0 ac19 p_ad<55> 193/194 0 aa19 p_ad<54> 194/195 0 table 39. boundary scan order (sheet 2 of 3) pin number signal name boundary scan order by group disable group disable cell
21154 pci-to-pci bridge specification update intel confidential27 documentation changes ab20 p_ad<53> 195/196 0 y19 p_ad<52> 196/197 0 aa20 p_ad<51> 197/198 0 ab21 p_ad<50> 198/199 0 ac21 p_ad<49> 199/200 0 aa21 p_ad<48> 200/201 0 y20 p_ad<47> 201/202 0 aa23 p_ad<46> 202/203 0 y21 p_ad<45> 203/204 0 w20 p_ad<44> 204/205 0 y23 p_ad<43> 205/206 0 w21 p_ad<42> 206/207 0 w23 p_ad<41> 207/208 0 w22 p_ad<40> 208/209 0 v21 p_ad<39> 209/210 0 v23 p_ad<38> 210/211 0 v22 p_ad<37> 211/212 0 u23 p_ad<36> 212/213 0 u20 p_ad<35> 213/214 0 u22 p_ad<34> 214/215 0 u21 v ss 215/216 ? group disable 0 t23 p_ad<33> 216/217 0 t22 p_ad<32> 217/218 0 t21 p_par64 218/219 0 r22 config66 219/220 ? r21 msk_in 220/221 ? table 39. boundary scan order (sheet 3 of 3) pin number signal name boundary scan order by group disable group disable cell
28intel confidential 21154 pci-to-pci bridge specification update documentation changes 6. section 4.3, paragraph 1 section 4.3, paragraph 1 is changed to read as follows: some versions of the 21154 support 66 mhz operation. versions marked 21154ax are not tested to be 66 mhz capable. versions of the 21154 marked 21154bx are capable of 66 mhz operation. 7. section 16.7, initialization, paragraph 1 this section has been changed to: the test access port controller and the instruction re gister output latches are initialized and jtag is disabled while the trst_l input is asserted low. while signal trst_l is low, the test access port controller enters the test-logic reset state. this results in the instruction register being reset which holds the bypass register instruction. during test-logic reset st ate, all jtag test logic is disabled and the device performs normal functions. the test access port controller leaves this state only after trst_l (low) goes high and an appropriate jtag test operation sequence is sent on the tms and tck pins. for the 21154 to operate properly, the jtag logic mu st be reset. there are two ways to reset this logic: ? the controller will reset asynchronously with the assertion of trst_l. ? the controller will reset synchronously after five tck clock cycles, with tms held high. note: during normal 21154 operation the jtag logic must be disabled by pulling trst_l low using a 5k resistor. 8. section 5.1, initialization, description this section has been changed to: the test access port controller and the instruction re gister output latches are initialized and jtag is disabled while the trst_l input is asserted low (see figure 5). while signal trst_l is low, the test access port controller enters the test-logic reset stat e. this results in the instruction register being reset which holds the bypass register instruction. during test-logic reset state, all jtag test logic is disabled, and the device performs normal functions. th e test access port controller leaves this state only after trst_l (low) goes high and an appropriate jtag test operation sequence is sent on the tms and tck pins. for the 21154 to operate properly, the jtag logic mu st be reset. there are two ways to reset this logic: ? the controller will reset asynchronously with the assertion of trst_l. ? the controller will reset synchronously after five tck clock cycles, with tms held high.. note: during normal 21154 operation the jtag logic must be disabled by pulling trst_l low using a 5k ohm resistor. figure 5. signal trst_l states a7805-01 trst_l jtag reset jtag enabled
21154 pci-to-pci bridge specification update intel confidential29 documentation changes 9. section 6.3.1, signal trst_l pull-down resistor, new section the following new section has been added: a 5 k ? pull-down resistor is required on trst_l for normal pci-to-pci bridge operation. however, some jtag test results may be inconclusive if the 5 k ? resistor remains in the circuit. to obtain accurate jtag results, intel recommends one of the following solutions: ? verify that the jtag test equipment, after driving trst_l low to reset the tap controller, constantly drives trst_l high during jtag tests. if this signal is not constantly driven high, the 5 k ? resistor will pull the signal to a low state. ? remove the 5 k ? resistor during jtag tests. this resistor must be installed during normal pci-to-pci bridge operation. ? design external circuits with a switch or jumper to isolate the 5 k ? resistor during jtag tests (see figure 6). this switch must enable the resistor during normal pci-to-pci bridge operation. 10. section 2.10, jtag signals, table 13 the description for trst_l has been changed as follows: figure 6. removal of pull-down resistor for jtag testing a7821-01 21154 50k ? v dd 5k ? switch or jumper trst_l table 13. jtag signals signal name type description tdi i jtag serial data in. signal tdi is the serial input through which jtag instructions and test data enter the jtag interface. the new data on tdi is sampled on the rising edge of tck. an unterminated tdi is pulled high by a weak pull-up resistor internal to the device. tms i jtag test mode select. signal tms causes state transitions in the test access port (tap) controller. an unterminated tms is pulled high by a weak pull-up resistor internal to the device. trst_l i jtag tap reset and disable. when asserted low, jtag is disabled and the tap controller is asynchronously forced to enter a reset state, which in turn asynchronously initializes other test logic. an unterminated trst_l is pulled high by a weak pull-up resistor internal to the device. the tap controller must be reset before the jtag circuits can function. for normal jtag tap port operation, this signal must be high. for normal pci-to-pci bridge operation of the device, this signal must be pulled low using a 5k resistor.
30intel confidential 21154 pci-to-pci bridge specification update documentation changes 11. section 5.0, system initialization, last paragraph the last paragraph in this section has been changed to: for information on initializing jtag, see the 21154 pci-to-pci bridge hardware implementation application note . 12. section 10.2, secondary clock control, figure 19 this figure now appears as follows: 13. section 10.2, secondary clock control, figure 20 this figure now appears as follows: figure 19 example of gpio clock mask implementation on the system board a7804-02 21154 74f166 ce# cp mr# pe# prsnto#<0> prsnto#<1> prsnto#<0> prsnto#<1> prsnto#<0> prsnto#<1> prsnto#<0> prsnto#<1> ds d7 msk_in s_clk_<9> gpio<0> gpio<2> v ss v ss d6 d5 d4 d3 d2 d1 d0 74f166 v cc v cc q7 q7 ce# cp mr# pe# d7 d6 d5 d4 d3 d2 d1 d0 figure 20. clock mask and load shift timing a7803-01 gpio[0] gpio[2] msk_in bit 15 bit 14
21154 pci-to-pci bridge specification update intel confidential31 documentation changes 14. section 10.2, secondary clock control, table 34 this table has been re-arranged to indicate the gpio serial data format. it now appears as follows: 15. section 10.2.1, mask and load shift timing events for 66 mhz operation the following new section has been added: the following list provides the timing sequence fo r 66 mhz operation for an example circuit as shown in figure 19 and the timing diagram in figure 21. 1. the gpio<2> original coming from the 21154 does not provide 3ns setup time needed to provide the parallel load enable pe# of the 74f166. 2. the shifted gpio<2> is delayed by ~9ns to provide ample setup time to enable the parallel of the shift register connected to pin 15 of the 74f166. 3. bit 15 input d6 of the shift register is pulled high, to vcc. 4. bit 14 input d7 is pulled high, to vcc. these signals are not used internally in the 21154. 5. bit 13 s_clk_o<9> is a feedback to the 21154 s_clk_o input. to enable s_clk_o<9> in all cases the d5 input of the shift register is grounded, to vss. 6. bit 12 s_clk_o<8> is disabled. 7. bit 11 s_clk_o<7> is disabled. 8. bit 10 s_clk_o<6> is disabled. 9. bit 9 s_clk_o<5> is disabled. table 34. gpio serial data format bit description s_clk_o output <15:14> reserved not applicable <13> 21154 s_clk input 9 <12> device 8 8 <11> device 7 7 <10> device 6 6 <9> device 5 5 <8> device 4 4 <7:6> slot 3 prsnt#<1:0> or device 3 3 <5:4> slot 2 prsnt#<1:0> or device 2 2 <3:2> slot 1 prsnt#<1:0> or device 1 1 <1:0> slot 0 prsnt#<1:0> or device 0 0
32intel confidential 21154 pci-to-pci bridge specification update documentation changes 16. section 15.1.3, primary command register, table description changed the description in dword 0 for when it is a one. it now appears as follows: figure 21. clock mask and load shift timing a8798-01 1 3 4 5 6 7 8 9 2 gpio<0> gpio<2> shifted gpio<2> msk_in primary command register dword bit name r/w description 0 i/o space enable r/w controls the 21154?s response to i/o transactions on the primary interface. 0 = the 21154 does not respond to i/o transactions initiated on the primary bus. 1 = the 21154 response to i/o transactions initiated on the primary bus is in the enabled state. reset value: 0.
21154 pci-to-pci bridge specification update intel confidential33 documentation changes 17. section 4.4.1, serial clock mask shift, table 4 table 4 has been changed as follows: 18. section 4.4.1, serial clock mask shift, figure 3 figure 3 has been updated as follows: table 4. gpio serial data format bit description s_clk_o output <15> reserved not applicable <14> reserved not applicable <13> 21154 s_clk input 9 <12> device 8 8 <11> device 7 7 <10> device 6 6 <9> device 5 5 <8> device 4 4 <7:6> slot 3 prsnt#<1:0> or device 3 3 <5:4> slot 2 prsnt#<1:0> or device 2 2 <3:2> slot 1 prsnt#<1:0> or device 1 1 <1:0> slot 0prsnt#<1:0> or device 0 0
34intel confidential 21154 pci-to-pci bridge specification update documentation changes 19. section 4.4.1, serial clock mask shift, figure 4 figure 4 now appears as follows: 20. section 4.2, 21154 output clocks this note has been added to the end of the section: note: intel recommends that a 22k pull-up resistor be placed on s_clk to better insure proper initialization on power-up. figure 3 example of gpio clock mask implementation on the system board a7804-02 21154 74f166 ce# cp mr# pe# prsnto#<0> prsnto#<1> prsnto#<0> prsnto#<1> prsnto#<0> prsnto#<1> prsnto#<0> prsnto#<1> ds d7 msk_in s_clk_<9> gpio<0> gpio<2> v ss v ss d6 d5 d4 d3 d2 d1 d0 74f166 v cc v cc q7 q7 ce# cp mr# pe# d7 d6 d5 d4 d3 d2 d1 d0 figure 4. clock mask load and shift timing a7803-01 gpio[0] gpio[2] msk_in bit 15 bit 14
21154 pci-to-pci bridge specification update intel confidential35 documentation changes 21. section 18.0, table 51, 304-point 2-layer pbga package dimensions the maximum value for symbol aaa, dimension copl anarity has been changed from 0.15 mm to a value of 0.2 mm. 22. section 2.5, secondary bus arbitration signals, table 8 this sentence is added to the end of the description for s_req_l <8:0>: ?when the secondary bus is set to operate at 66 mhz, s_req_l <8:4> is disabled.? this sentence is added to the end of the description for s_gnt_l<8:0>: ?when the secondary bus is set to operate at 66 mhz, s_gnt_1 <8:4> is disabled.? 23. section 2.9, miscellaneous signals, table 12 this sentence is added at the end of the description for s_m66ena: ?when the secondary bus is set to operate at 66 mhz, s_req_l <8:4> and s_gnt_1<8:4> are disabled.? 24. updated version of pci local bus specification all places in the 21154 hardware bridge hardware implementation application note where the pci local bus specification is mentioned was updated from version 2.1 to version 2.2. 25. section 4.1, updated s_clk and p_clk description the first two paragraphs and the first bull et in section 4.1 now appear as follows: 4.1 21154 clocking domains the 21154 has two clocking domains: one for the primary pci interface and one for the secondary pci interface. each pci interface has a separate cl ock input. the primary interface is controlled by the primary clock input, p_clk, and the secondar y interface and arbiter is controlled by the secondary clock input, s_clk. the edge relationship between s_clk and p_clk is well defined. the relationship between the p_clk and s_clk inputs has the following restrictions: ? the 21154 operates at a maximum frequency of 66 mhz, and s_clk always operates at the same frequency or half the frequency of p_clk. 26. section 4.2, updated clock outputs the first bulleted item in section 4.2 now appears as follows: ? all clock outputs operate at the same or half the frequency as p_clk. 27. section 4.4.1, added note at end of section. the note added to the end of section 4.4.1 appears as follows: note: refer to errata #7 previously in this document for an explanation of an added external buffer on the output of gpio <2> to use this feature at 66 mhz.
36intel confidential 21154 pci-to-pci bridge specification update documentation changes 28. section 4.5, table 5 product part numbers have been updated. table 5 now appears as follows: table 5. low-skew clock buffers 29. updated version of pci local bus specification all references in the 21154 pci-to-pci bridge documentation where the pci local bus specification is mentioned were updated from version 2.2 to version 2.3. vendor part number (5v) part number (3.3v) texas instruments cdc328a cdcv304 national semiconductor cgs74b2525 cgs574ct2524 idc 1dt74fct805ct qs53805

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